000 | 00376nam a2200145Ia 4500 | ||
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999 |
_c178195 _d178195 |
||
020 | _a9789381269220 | ||
040 | _cCUS | ||
082 |
_a004.22 _bHEN/C |
||
245 | 0 |
_aComputer architecture/ _ba quantitative approach _cHennessy,John L. |
|
250 | _a5 | ||
260 |
_aNew Delhi: _bElsevier, _c2012. |
||
300 | _a493 | ||
505 | _aPrinted Text Chap 1: Fundamentals of Quantitative Design and Analysis Chap 2: Memory Hierarchy Design Chap 3: Instruction-Level Parallelism and Its Exploitation Chap 4: Data-Level Parallelism in Vector, SIMD, and GPU Architectures Chap 5: Multiprocessors and Thread-Level Parallelism Chap 6: The Warehouse-Scale Computer App A: Instruction Set Principles App B: Review of Memory Hierarchy App C: Pipelining: Basic and Intermediate Concepts Online App D: Storage Systems App E: Embedded Systems App F: Interconnection Networks App G: Vector Processors App H: Hardware and Software for VLIW and EPIC App I: Large-Scale Multiprocessors and Scientific Applications App J: Computer Arithmetic App K: Survey of Instruction Set Architectures App L: Historical Perspectives | ||
942 | _cWB16 |