ARM system developer's guide: designing and optimizing system software/ Andrew N Sloss

ARM Embedded Systems
1.1 The RISC Design Philosophy
1.2 The
ARM Design Philosophy
1.3 Embedded System Hardware
1.4 Embedded System Software
1.5 Summary
ARM Processor Fundamentals
2.1 Registers
2.2 Current Program Status Register
2.3 Pipeline
2.4 Exceptions, Interrupts, and the Vector Table
2.5 Core Extensions
2.6 Architecture Revisions
2.7 ARM Processor Families
2.8 Summary
Introduction to the ARM Instruction Set
3.1 Data Processing Instructions
3.2 Branch Instructions
3.3 Load-Store Instructions
3.4 Software Interrupt Instruction
3.5 Program Status Register Instructions
3.6 Loading Constants
3.7 ARMv5E Extensions
3.8 Conditional Execution
3.9 Summary
Introduction to the Thumb Instruction Set
4.1 Thumb Register Usage
4.2 ARM-Thumb Interworking
4.3 Other Branch Instructions
4.4 Data Processing Instructions
4.5 Single-Register Load-Store Instructions
4.6 Multiple-Register Load-Store Instructions
4.7 Stack Instructions
4.8
Software Interrupt Instruction
4.9
Summary
Efficient C programming
5.1
Overview ofC Compilers and Optimization
5.2 Basic C Data Types
5.3 C Looping Structures
113
5.4
Register Allocation
120
5.5
Function Calls
5.6
Pointer Aliasmg
5.7
Structure Arrangement
5.8
Bit-fields
5.9
Unaligned Data and Endianness
5.10
Division
5.11
Floating Point
5.12
Inline Functions and Inline Assembly
149
5.13
Portability Issues
5.14
Summary
Writing and Optimizing ARM Assembly Code
6.1 Writing Assembly Code
6.2 Profiling and CycleCounting
6.3 Instruction Scheduling
6.4 Register Allocation
6.5 Conditional Execution
6.6 Looping Constructs
6.7 Bit Manipulation
6.8 Efficient Switches

6.9 Handling Unaligned Data
6.10 Summary
Optimized Primitives
7.1 Double-Precision Integer Multiplication
7.2 Integer Normalization And Count Leading Zeros
7.3 Division
7.4 Square Roots
7.5 Transcendental Functions: log, exp, sin, cos
7.6 Endian Reversal and Bit Operations
7.7 Saturated and Rounded Arithmetic
7.8 Random Number Generation
7.9 Summary
Digital Signal Processing
8.1 Representing a Digital Signal
8.2 Introduction to DSP on the ARM
8.3 FIR filters
8.4 IIR Filters
8.5 The Discrete Fourier Transform
8.6 Summary
Exception and Interrupt Handling
9.1 Exception Handling
9.2 Interrupts
9.3 Interrupt HandlingSchemes
9.4 Sunmiary
Firmware
10.1 Firmware and Bootloader
10.2 Example:Sandstone
10.3 Summary

14
Embedded Operating Systems
381
11.1 Fundamental Components
381
11.2 Example: Simple Little Operating System
383
11.3 Summary
Caches
403
12.1 The Memory Hierarchy and Cache Memory
404
12.2 Cache Architecture
408
12.3 Cache Policy
418
12.4 Coprocessor 15 and Caches
423
12.5 Flushing and Cleaning Cache Memory
423
12.6 Cache Lockdown
443
12.7 Caches and Software Performance
456
12.8 Summary
457
Memory Protection Units
461
13.1 Protected Regions
463
13.2 Initializing the MPU, Caches, and Write Buffer 465
13.3 Demonstration of an MPU system
478
13.4 Summary
487
Memory Management Units
491
14.1 Moving from an MPU to an MMU
14.2 How Virtual Memory Works
14.3 Details of the ARM MMU
14.4 PageTables
14.5 The Translation Lookaside Buffer
14.6 Domains and Memory Access Permission
14.7 The Caches and Write Buffer
14.8 Coprocessor 15 and MMU Configuration
14.9 The Fast Context Switch Extension
14.10 Demonstration: A Small Virtual Memory System
14.11 The Demonstration as mmu SLOS
14.12 Summary
Appendix
The Future of the Architecture
BY John Rayfield
15.1 Advanced DSP and SIMD Support in ARMv6
15.2 System and Multiprocessor SupportAdditions to ARMv6
15.3 ARMv6 Implementations
15.4 Future Technologiesbeyond ARMv6
15.5 Summary
A
ARM AND Thumb Assembler Instructions
Appendix
A,1 Using This Appendix
A.2 Syntax
A.3 Alphabetical List o fARM and Thumb Instructions
A.4 ARM Assembler Quick Reference
A.5
GNU Assembler Quick Reference
B
ARM AND Thumb Instruction Encodings
Appendix
B.1 ARMInstruction Set Encodings
B.2 Thumb Instruction Set Encodings
B.3 Program Status Registers
c
Processors and Architecture
Appendix
C.1 ARMN aming Convention
C.2 Core and Architectures
D
Instruction Cycle Timings
D.1 Using the Instruction Cycle Timing Tables
D.2 ARM7TDMI Instruction Cycle Timings
D.3 ARM9TDMI Instruction Cycle Timings
D.4 Strong ARMl Instruction Cycle Timings
D.5 ARM9E Instruction Cycle Timings
D.6
ARM1OE Instruction Cycle Timings
D.7 IntelXS cale Instruction Cycle Timings
D.8 ARMll CycleTimings