Computer architecture/  a quantitative approach 
Hennessy,John L. 
 - 5 
 - New Delhi:  Elsevier,  2012. 
 - 493 
<br/><br/>Printed Text Chap 1: Fundamentals of Quantitative Design and Analysis <br/>Chap 2: Memory Hierarchy Design <br/>Chap 3: Instruction-Level Parallelism and Its Exploitation Chap 4: Data-Level Parallelism in Vector, SIMD, and GPU Architectures <br/>Chap 5: Multiprocessors and Thread-Level Parallelism <br/>Chap 6: The Warehouse-Scale Computer <br/>App A: Instruction Set Principles <br/>App B: Review of Memory Hierarchy <br/>App C: Pipelining: Basic and Intermediate Concepts Online <br/>App D: Storage Systems <br/>App E: Embedded Systems <br/>App F: Interconnection Networks <br/>App G: Vector Processors <br/>App H: Hardware and Software for VLIW and EPIC <br/>App I: Large-Scale Multiprocessors and Scientific Applications App J: Computer Arithmetic <br/>App K: Survey of Instruction Set Architectures <br/>App L: Historical Perspectives 
<br/><br/><label>ISBN: </label>9789381269220 
<br/><br/><label>Dewey Class. No.: </label>004.22  / HEN/C