Computer systems design and architecture / Vincent P. Heuring, Harry F. Jordan a contri and T.G. Venkatesh

By: Heuring, Vincent PMaterial type: TextTextPublication details: Upper Saddle River, N.J. : Pearson/Prentice Hall, 2004Edition: 2nd edDescription: xvi, 592 p 25 cm. illISBN: 0130484407; 9780130484406Subject(s): System Design | Computer ArchitectureDDC classification: 004.22
Contents:
CHAPTER 1 The General Purpose Machine The General Purpose Machine 2 The User's View 3 The Machine/Assembly Language Programmer's View 5 The Computer Architect's View 11 The Computer System Logic Designer's View 16 Historical Perspective 19 Trends and Research 23 Approach of the Text 24 Summary 25 Bibliography 26 Exercises 26 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 CHAPTER 2 Machines, Machine Langui^es, and Digital Logic Classification of Computers and Their Instructions 30 Computer Instruction Sets 32 Informal Description of the Simple RISC Computer, SRC 47 Formal Description of SRC Using Register Transfer Notation, RTN Describing Addressing Modes with RTN 64 Register Transfers and Logic Circuits: From Behavior to Hardware Summary 77 Bibliography 78 Exercises 79 2.1 2.2 2.3 2.4 2.5 2.6 55 66 CHAPTER 3 Some Real Machines 3.1 3.2 Machine Characteristics and Performance RISC versus CISC 88 84 3.3 A CISC Microprocessor: The Motorola MC68000 93 3.4 A RISC Architecture: The SPARC 117 3.5 More CISC and RISC Processors 132 3.6 Digital Signal Processors 137 Summary 141 Bibliography 142 Exercises 143 CHAPTER 4 Processor Design 4.1 The Design Process 148 4.2 A 1-Bus Microarchitecture for the SRC 149 4.3 Data Path Implementation 154 4.4 Logic Design for the 1-Bus SRC 155 4.5 The Control Unit 167 4.6 The 2-and 3-Bus Processor Designs 175 4.7 The Machine Reset 181 4.8 Machine Exceptions 183 4.9 Microprogramming 191 Summary 205 Bibliography 206 Exercises 206 chapter 5 Processor Design—^Exploiting Parallelism 5.1 Pipelining Overview 212 5.2 Design of Linear Pipeline 214 5!3 Design of Static and Dynamic Multifunction Non-Linear Pipeline 5.4 Design of Instruction Pipeline 239 5.5 Pipeline Hazards 256 5.6 Instruction-Level Parallelism 280 Summary 303 Bibliography 303 Exercises 304 CHAPTER 6 Computer Arithmetic and the Arithmetic Unit 6.1 Number Systems and Radix Conversion 311 6.2 Fixed-Point Arithmetic 322 6.3 Seminumeric Aspects of ALU Design 356 6.4 Floating-Point Arithmetic 362 Summary 371 Bibliography 371 Exercises 372 CHAPTER 7 Memory System Design 7.1 Introduction: The Components of the Memory System 378 7.2 RAM Structure: The Logic Designer's Perspective 381 7.3 Memory Boards and Modules 397 7.4 Memory Hierarchy 416 7.5 The Cache 422 7.6 Virtual Memory 444 7.7 The Memory Subsystem in the Computer 465 Summary 467 Bibliography 468 Exercises 468 CHAPTER 8 Input aud Output 8.1 The I/O Subsystem 474 8.2 Programmed I/O 477 8.3 I/O Interrupts 486 8.4 Direct Memory Access (DMA) 494 '8.5 I/O Data Format Change and Error Control 497 Summary 503 Bibliography 504 Exercises 504 CHAPTER 9 System Software Architectures 9.1 Operating System 507 9.2 Compilers, Loaders, and Linkers 521 9.3 Assembly and Assemblers 525 Summary 535 Bibliography 535 CHAPTER 10 Peripheral Devices 10.1 Magnetic Disk Drives 538 10.2 Improving Disk System Performance and Reliability 547 10.3 Other Mass Storage Devices 549 10.4 Display Devices 550 10.5 Printers 558 10.6 Input Devices 560 10.7 Interfacing to the Analog World 561 Summary 565 Bibliography 566 Exercises 566 CHAPTER 11 Conununications, Networking, and the Internet 11.1 Computer to Computer Data Communications 570 11.2 Serial Data Communications Protocols 578 11.3 Local Area Networks 584 11.4 Modern Serial Buses: USB and FireWire 587 11.5 The Internet 591 Summary 601 Bibliography 602 Exercises 603 CHAPTER 12 Parallel Processing 12.1 Taxonomy of Parallel Architectures 606 12.2 Vector Supercomputers 607 12.3 SIMD Array Processors 609 12.4 Shared Memory Multiprocessor 611 12.5 Interconnection Networks (IN) 612 12.6 The Systolic Array Processors 619 Bibliography 625 Exercises 625
Tags from this library: No tags from this library for this title. Log in to add tags.
Star ratings
    Average rating: 0.0 (0 votes)
Holdings
Item type Current library Call number Status Date due Barcode Item holds
General Books General Books Central Library, Sikkim University
General Book Section
004.22 HEU/C (Browse shelf(Opens below)) Available P18721
Total holds: 0

CHAPTER 1 The General Purpose Machine
The General Purpose Machine 2
The User's View 3
The Machine/Assembly Language Programmer's View 5
The Computer Architect's View 11
The Computer System Logic Designer's View 16
Historical Perspective 19
Trends and Research 23
Approach of the Text 24
Summary 25
Bibliography 26
Exercises 26
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
CHAPTER 2 Machines, Machine Langui^es, and Digital Logic
Classification of Computers and Their Instructions 30
Computer Instruction Sets 32
Informal Description of the Simple RISC Computer, SRC 47
Formal Description of SRC Using Register Transfer Notation, RTN
Describing Addressing Modes with RTN 64
Register Transfers and Logic Circuits: From Behavior to Hardware
Summary 77
Bibliography 78
Exercises 79
2.1
2.2
2.3
2.4
2.5
2.6
55
66
CHAPTER 3 Some Real Machines
3.1
3.2
Machine Characteristics and Performance
RISC versus CISC 88
84
3.3 A CISC Microprocessor: The Motorola MC68000 93
3.4 A RISC Architecture: The SPARC 117
3.5 More CISC and RISC Processors 132
3.6 Digital Signal Processors 137
Summary 141
Bibliography 142
Exercises 143
CHAPTER 4 Processor Design
4.1 The Design Process 148
4.2 A 1-Bus Microarchitecture for the SRC 149
4.3 Data Path Implementation 154
4.4 Logic Design for the 1-Bus SRC 155
4.5 The Control Unit 167
4.6 The 2-and 3-Bus Processor Designs 175
4.7 The Machine Reset 181
4.8 Machine Exceptions 183
4.9 Microprogramming 191
Summary 205
Bibliography 206
Exercises 206
chapter 5 Processor Design—^Exploiting Parallelism
5.1 Pipelining Overview 212
5.2 Design of Linear Pipeline 214
5!3 Design of Static and Dynamic Multifunction Non-Linear Pipeline
5.4 Design of Instruction Pipeline 239
5.5 Pipeline Hazards 256
5.6 Instruction-Level Parallelism 280
Summary 303
Bibliography 303
Exercises 304
CHAPTER 6 Computer Arithmetic and the Arithmetic Unit
6.1 Number Systems and Radix Conversion 311
6.2 Fixed-Point Arithmetic 322
6.3 Seminumeric Aspects of ALU Design 356
6.4 Floating-Point Arithmetic 362
Summary 371
Bibliography 371
Exercises 372
CHAPTER 7 Memory System Design
7.1 Introduction: The Components of the Memory System 378
7.2 RAM Structure: The Logic Designer's Perspective 381
7.3 Memory Boards and Modules 397
7.4 Memory Hierarchy 416
7.5 The Cache 422
7.6 Virtual Memory 444
7.7 The Memory Subsystem in the Computer 465
Summary 467
Bibliography 468
Exercises 468
CHAPTER 8 Input aud Output
8.1 The I/O Subsystem 474
8.2 Programmed I/O 477
8.3 I/O Interrupts 486
8.4 Direct Memory Access (DMA) 494
'8.5 I/O Data Format Change and Error Control 497
Summary 503
Bibliography 504
Exercises 504
CHAPTER 9 System Software Architectures
9.1 Operating System 507
9.2 Compilers, Loaders, and Linkers 521
9.3 Assembly and Assemblers 525
Summary 535
Bibliography 535
CHAPTER 10 Peripheral Devices
10.1 Magnetic Disk Drives 538
10.2 Improving Disk System Performance and Reliability 547
10.3 Other Mass Storage Devices 549
10.4 Display Devices 550
10.5 Printers 558
10.6 Input Devices 560
10.7 Interfacing to the Analog World 561
Summary 565
Bibliography 566
Exercises 566
CHAPTER 11 Conununications, Networking, and the Internet
11.1 Computer to Computer Data Communications 570
11.2 Serial Data Communications Protocols 578
11.3 Local Area Networks 584
11.4 Modern Serial Buses: USB and FireWire 587
11.5 The Internet 591
Summary 601
Bibliography 602
Exercises 603
CHAPTER 12 Parallel Processing
12.1 Taxonomy of Parallel Architectures 606
12.2 Vector Supercomputers 607
12.3 SIMD Array Processors 609
12.4 Shared Memory Multiprocessor 611
12.5 Interconnection Networks (IN) 612
12.6 The Systolic Array Processors 619
Bibliography 625
Exercises 625

There are no comments on this title.

to post a comment.
SIKKIM UNIVERSITY
University Portal | Contact Librarian | Library Portal

Powered by Koha