System Verilog for Verification: a Guide to Learning the Testbench Language Features / (Record no. 2674)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 05093cam a22002895i 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780387765303 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781441945617 (print) |
| 040 ## - CATALOGING SOURCE | |
| Transcribing agency | CUS |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 005.14 |
| Item number | SPE/S |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Spear, Chris. |
| 245 10 - TITLE STATEMENT | |
| Title | System Verilog for Verification: a Guide to Learning the Testbench Language Features / |
| Statement of responsibility, etc. | Chris Spear. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 2nd ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc. | New York : |
| Name of publisher, distributor, etc. | Springer , |
| Date of publication, distribution, etc. | 2008. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xxvi, 429 p. |
| 505 ## - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 1. VERIFICATION GUIDELINES<br/>1.1 The Verification Process<br/>1.2 The Verification Methodology Manual<br/>1.3 Basic Testbench Functionality<br/>1.4 Directed Testing<br/>1.5 Methodology Basics<br/>1.6 Constrained-Random Stimulus<br/>1.7 What Should You Randomize?<br/>1.8 Functional Coverage<br/>1.9 Testbench Components<br/>1.10 Layered Testbench<br/>1.11 Building a Layered Testbench<br/>1.12 Simulation Environment Phases<br/>1.13 Maximum Code Reuse<br/>1.14 Testbench Performance<br/>1.15 Conclusion<br/>2. DATA TYPES<br/>2.1 Built-in Data Types<br/>2.2 Fixed-Size Arrays<br/>2.3 Dynamic Arrays<br/>2.4 Queues<br/>2.5 Associative Arrays<br/>2.6 Linked Lists<br/>2.7 Array Methods<br/>2.8 Choosing a Storage Type<br/>2.9 Creating New Types with typedef<br/>2.10 Creating User-Defined Structures<br/>2.11 Type conversion<br/>2.12 Enumerated Types<br/>2.13 Constants<br/>2.14 Strings<br/>2.15 Expression Width<br/>2.16 Conclusion<br/>3. PROCEDURAL STATEMENTS<br/>AND ROUTINES<br/>3.1 Procedural Statements<br/>3.2 Tasks, Functions, and Void Functions<br/>3.3 Task and Function Overview<br/>3.4 Routine Arguments<br/>3.5 Returning from a Routine<br/>3.6 Local Data Storage<br/>3.7 Time Values<br/>3.8 Conclusion<br/>4. CONNECTING THE TESTBENCH<br/>AND DESIGN<br/>4.1 Separating the Testbench and Design<br/>4.2 The Interface Construct<br/>4.3 Stimulus Timing<br/>4.4 Interface Driving and Sampling<br/>4.5 Connecting It All Together<br/>4.6 Top-Level Scope<br/>4.7 Program - Module Interactions<br/>4.8 SystemVerilog Assertions<br/>4.9 The Four-Port ATM Router<br/>4.10 The ref Port Direction<br/>4.11 The End of Simulation<br/>4.12 Directed Test for the LC3 Fetch Block<br/>4.13 Conclusion<br/>5. BASIC OOP<br/>5.1 Introduction<br/>5.2 Think of Nouns, not Verbs<br/>5.3 Y our F irst Class<br/>5.4 Where to Define a Class<br/>5.5 OOP Terminology<br/>5.6 Creating New Objects<br/>5.7 Object Deallocation<br/>5.8 Using Objects<br/>5.9 Static Variables vs. Global Variables<br/>5.10 Class Methods<br/>5.11 Defining Methods Outside of the Class<br/>5.12 Scoping Rules<br/>5.13 Using One Class Inside Another<br/>5.14 Understanding Dynamic Objects<br/>5.15 Copying Objects<br/>5.16 Public vs. Local<br/>5.17 Straying Off Course<br/>5.18 Building a Testbench<br/>5.19 Conclusion<br/>6. RANDOMIZATION<br/>6.1 Introduction<br/>6.2 What to Randomize<br/>6.3 Randomization in SystemVerilog<br/>6.4 Constraint Details<br/>6.5 Solution Probabilities<br/>6.6 Controlling Multiple Constraint Blocks<br/>i 6.7 Valid Constraints<br/>7.<br/>6.8 In-line Constraints<br/>6.9 The pre randomize and post randomize Functions<br/>6.10 Random Number Functions<br/>6.11 Constraints Tips and Techniques<br/>6.12 Common Randomization Problems<br/>6.13 Iterative and Array Constraints<br/>6.14 Atomic Stimulus Generation vs. Scenario Generation<br/>6.15 Random Control<br/>6.16 Random Number Generators<br/>6.17 Random Device Configuration<br/>6.18 Conclusion<br/>THREADS AND INTERPROCESS COMMUNICATION<br/>7.1 Working with Threads<br/>7.2 Disabling Threads<br/>7.3 Interprocess Communication<br/>7.4 Events<br/>7.5 Semaphores<br/>7.6 Mailboxes<br/>7.7 Building a Testbench with Threads and IPC<br/>7.8 Conclusion<br/>8. ADVANCED OOP AND TESTBENCH GUIDELINES<br/>8.1 Introduction to Inheritance<br/>8.2 Blueprint Pattern<br/>8.3 Downcasting and Virtual Methods<br/>8.4 Composition, Inheritance, and Alternatives<br/>8.5 Copying an Object<br/>8.6 Abstract Classes and Pure Virtual Methods<br/>8.7 Callbacks<br/>8.8 Parameterized Classes<br/>8.9 Conclusion<br/>9. FUNCTIONAL COVERAGE<br/>9.1 Coverage Types<br/>9.2 Functional Coverage Strategies<br/>9.3 Simple Functional Coverage Example<br/>9.4 Anatomy of a Cover Group<br/>9.5 Triggering a Cover Group<br/>9.6 Data Sampling<br/>9.7 Cross Coverage<br/>9.8 Generic Cover Groups<br/>9.9 Coverage Options<br/>9.10 Analyzing Coverage Data<br/>9.11 Measuring Coverage Statistics During Simulation<br/>9.12 Conclusion<br/>10. ADVANCED INTERFACES<br/>10.1 Virtual Interfaces with the ATM Router<br/>10.2 Connecting to Multiple Design Configurations<br/>10.3 Procedural Code in an Interface<br/>10.4 Conclusion<br/>11. A COMPLETE SYSTEMVERILOG<br/>TESTBENCH<br/>1 1.1 Design Blocks<br/>1 1.2 Testbench Blocks<br/>1 1.3 Alternate Tests<br/>|]4 Conclusion<br/>12. INTERFACING WITH C<br/>12.1 Passing Simple Values<br/>12.2 Connecting to a Simple C Routine<br/>12.3 Connecting to C++<br/>12.4 Simple Array Sharing<br/>12.5 Open arrays<br/>12.6 Sharing Composite Types<br/>12.7 Pure and Context Imported Methods<br/>12.8 Communicating from C to SystemVerilog<br/>12.9 Connecting Other Languages<br/>12.10 Conclusion |
| 650 #0 - SUBJECT | |
| Keyword | Engineering. |
| 650 #0 - SUBJECT | |
| Keyword | Computer hardware. |
| 650 #0 - SUBJECT | |
| Keyword | Computer aided design. |
| 650 #0 - SUBJECT | |
| Keyword | Computer engineering. |
| 650 #0 - SUBJECT | |
| Keyword | Systems engineering. |
| 650 14 - SUBJECT | |
| Keyword | Engineering. |
| 650 24 - SUBJECT | |
| Keyword | Circuits and Systems. |
| 650 24 - SUBJECT | |
| Keyword | Computer-Aided Engineering (CAD, CAE) and Design. |
| 650 24 - SUBJECT | |
| Keyword | Computer Hardware. |
| 650 24 - SUBJECT | |
| Keyword | Electrical Engineering. |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | General Books |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Full call number | Accession number | Date last seen | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Central Library, Sikkim University | Central Library, Sikkim University | General Book Section | 13/06/2016 | 005.14 SPE/S | P31285 | 13/06/2016 | General Books |