Computer architecture:a quantitative approach / (Record no. 1800)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 04286cam a2200169 a 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9789381269220 (pb) |
| 040 ## - CATALOGING SOURCE | |
| Transcribing agency | CUS |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 004.22 |
| Item number | HEN/C |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Hennessy, John L. |
| 245 10 - TITLE STATEMENT | |
| Title | Computer architecture:a quantitative approach / |
| Statement of responsibility, etc. | John L. Hennessy, David A. Patterson |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 5th ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc. | Amsterdam ; |
| -- | Boston : |
| Name of publisher, distributor, etc. | Morgan Kaufmann, |
| Date of publication, distribution, etc. | 2007. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 v. (various pagings) : |
| Dimensions | 24 cm. + |
| 505 ## - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Chapter 1 Fundamentals of Quantitative Design and Analysis<br/>1.1 Introduction<br/>1.2 Classes of Computers<br/>1.3 Defining Computer Architecture<br/>1.4 Trends in Technology<br/>1.5 Trends in Power and Energy in Integrated Circuits<br/>1.6 Trends in Cost<br/>1.7 Dependability<br/>1.8 Measuring, Reporting, and Summarizing Performance<br/>1.9 Quantitative Principles of Computer Design<br/>1.10 Putting It All Together; Performance, Price, and Power<br/>1.11 Fallacies and Pitfalls<br/>1.12 Concluding Remarks<br/>1.13 Historical Perspectives and References<br/>Case Studies and Exercises by Diana Franklin<br/>Chapter 2 Memory Hierarchy Design<br/>2.1 Introduction<br/>2.2 Ten Advanced Optimizations of Cache Performance<br/>2.3 Memory Technology and Optimizations<br/>2.4 Protection; Virtual Memory and Virtual Machines<br/>2.5 Crosscutting lssues; The Design of Memory Hierarchies<br/>2.6 Putting It All Together; Memory Hierachies in the<br/>ARM Cortex-A8 and Intel Core 17<br/>2.7 Fallacies and Pitfalls<br/>2.8 Concluding Remarks: Looking Ahead<br/>2.9 Historical Perspective and References<br/>Case Studies and Exercises by Norman P. Jouppi,<br/>Naveen Muralimanohar, and Sheng Li<br/>Chapter 3 Instruction-Level Parallelism and Its Exploitation<br/>3.1 Instruction-Level Parallelism: Concepts and Challenges<br/>3.2 Basic Compiler Techniques for Exposing ILP<br/>3.3 Reducing Branch Costs with Advanced Branch Prediction<br/>3.4 Overcoming Data Hazards with Dynamic Scheduling<br/>3.5 Dynamic Scheduling: Examples and the Algorithm<br/>3.6 Hardware-Based Speculation<br/>3.7 Exploiting ILP Using Multiple Issue and Static Scheduling<br/>3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and<br/>Speculation<br/>3.9 Advanced Techniques for Instruction Delivery and Speculation<br/>3.10 Studies of the Limitations of ILP<br/>3.11 Cross-Cutting Issues: ILP Approaches and the Memory System<br/>3.12 Multithreading: Exploiting Thread-Level Parallelism to Improve<br/>Uniprocessor Throughput<br/>3.13 Putting It All Together: The Intel Core 17 and ARM Cortex-A8<br/>3.14 Fallacies and Pitfalls<br/>3.15 Concluding Remarks: What's Ahead?<br/>3.16 Historical Perspective and References<br/>Case Studies and Exercises by Jason D. Bakos and Robert P. Colwell<br/>Chapter4 Data-Level Parallelism in Vector, SIMD, and GPU Architectures<br/>4.1 Introduction<br/>4.2 Vector Architecture<br/>4.3 SIMD Instruction Set Extensions for Multimedia<br/>4.4 Graphics Processing Units<br/>4.5 Detecting and Enhancing Loop-Level Parallelism<br/>4.6 Crosscutting Issues<br/>4.7 Putting It All Together: Mobile versus Server CPUs<br/>and Tesia versus Core 17<br/>4.8 Fallacies and Pitfalls<br/>4.9 Concluding Remarks<br/>4.10 Historical Perspective and References<br/>Case Study and Exercises by Jason D. Bakos<br/>Chapter 5 Thread-Level Parallelism<br/>5.1 Introduction<br/>Centralized Shared-Memory Architectures<br/>Performance of Symmetric Shared-Memory Multiprocessors<br/>5.2<br/>5.3<br/>5.4 Distributed Shared-Memory and Directory-Based Coherence<br/>5.5 Synchronization: The Basics<br/>5.6 Models of Memory Consistency: An Introduction<br/>5.7 Crosscutting Issues<br/>5.8 Putting It All Together: Multicore Processors and Their Performance<br/>5.9 Fallacies and Pitfalls<br/>5.10 Concluding Remarks<br/>5.11 Historical Perspectives and References<br/>Case Studies and Exercises by Amr Zaky and David A. Wood<br/>Chapter 6 Warehouse-Scale Computers to Exploit Request-Level and<br/>Data-Level Parallelism<br/>6.1 Introduction<br/>6.2 Programming Models and Workloads for Warehouse-Scale Computers<br/>6.3 Computer Architecture of Warehouse-Scale Computers<br/>6.4 Physical Infrastructure and Costs of Warehouse-Scale Computers<br/>6.5 Cloud Computing: The Return of Utility Computing<br/>6.6 Crosscutting Issues<br/>6.7 Putting It All Together: A Google Warehouse-Scale Computer<br/>6.8 Fallacies and Pitfalls<br/>6.9 Concluding Remarks<br/>6.10 Historical Perspectives and References<br/>Case Studies and Exercises by Parthasarathy Ranganathan |
| 650 #0 - SUBJECT | |
| Keyword | Computer Architecture. |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | General Books |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Full call number | Accession number | Date last seen | Date last checked out | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Central Library, Sikkim University | Central Library, Sikkim University | General Book Section | 01/06/2016 | 004.22 HEN/C | P33205 | 14/07/2018 | 14/07/2018 | General Books |