Computer system architecture / (Record no. 1791)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 08574cam a2200169 a 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 978813170070 (pb) |
| 040 ## - CATALOGING SOURCE | |
| Transcribing agency | CUS |
| 082 0# - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 004.22 |
| Item number | MAN/C |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Mano, M. Morris, |
| 245 10 - TITLE STATEMENT | |
| Title | Computer system architecture / |
| Statement of responsibility, etc. | M. Morris Mano. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 2nd ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc. | Englewood Cliffs, N.J. : |
| Name of publisher, distributor, etc. | Prentice-Hall, |
| Date of publication, distribution, etc. | 2007 p. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xii, 520 p.ill.: |
| Dimensions | 25 cm. |
| 505 ## - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Digital Logic Circuits<br/>1-1 Digital Computers<br/>1-2 Logic Gates<br/>1-3 Boolean Algebra<br/>Complement of a Function<br/>1-4 Map Simplification<br/>Product-of-Sums Simplification<br/>Don't-Care Conditions<br/>1-5 Combinational Circuits<br/>Half-Adder<br/>Full-Adder<br/>1-6 Flip-Flops<br/>SR Flip-Flop<br/>D Flip-Flop<br/>JK Flip-Flop<br/>T Flip-Flop<br/>Edge-Triggered Flip-Flops<br/>Excitation Tables<br/>1-7 Sequential Circuits<br/>Flip-Flop Input Equations<br/>State Table<br/>State Diagram<br/>Design Example<br/>Design Procedure<br/>Problems<br/>References<br/>Digital Components<br/>2-1 Integrated Circuits<br/>2-2 Decoders<br/>NAND Gate Decoder<br/>Decoder Expansion<br/>Encoders<br/>2-3 Multiplexers<br/>2-4 Registers<br/>Register with Parallel Load<br/>2-5 Shift Registers<br/>Bidirectional Shift Register with Parallel Load<br/>2-6 Binary Counters<br/>Binary Counter with Parallel Load<br/>2-7 Memory Unit<br/>Random-Access Memory<br/>Read-Only Memory<br/>Types of ROMs<br/>Problems<br/>References<br/>Data Representation<br/>3-1 Data Types<br/>Number Systems<br/>Octal and Hexadecimal Numbers<br/>Decimal Representation<br/>Alphanumeric Representation<br/>3-2 Complements<br/>(r — l)'s Complement<br/>(Ps) Complement<br/>Subtraction of Unsigned Numbers<br/>3-3 Fixed-Point Representation<br/>Integer Representation<br/>Aiidunetic Addition<br/>Arithmetic Subtraction<br/>Overflow t<br/>Decimal Fixed-Point Representation<br/>3-4 Floating-Point Representation<br/>3 "5 Other Binary Codes<br/>Gray Code<br/>Other Decimal Codes<br/>Other Alphanumeric Codes<br/>3 "6 Error Detection Codes<br/>Problems<br/>Register Transfer and Microoperations<br/>4" 1 Register Transfer Language<br/>4'2 Register Transfer<br/>4'3 Bus and Memory Transfers<br/>Three-State Bus Buffers<br/>Memory Transfer<br/>4'4 Arithmetic Microoperations<br/>Binary Adder<br/>Binary Adder-Subtractor<br/>Binary Incrementer<br/>Arithmetic Circuit<br/>4'5 Logic Microoperations<br/>List of Logic Microoperations<br/>Hardware Implementation<br/>Some Apphcations<br/>4-6 Shift Microoperations<br/>Hardware Implementation<br/>4-7 Arithmetic Logic Shift Unit<br/>4'8 Hardware Description Languages<br/>Introduction to VHDL<br/>Basic Framework and Syntax<br/>Problems<br/>Basic Computer Organization and Design<br/>5-1 Instruction Codes<br/>Stored Program Organization<br/>Indirect Address<br/>5 "2 Computer Registers<br/>Common Bus System<br/>5'3 Computer Instructions<br/>Instruction Set Completeness<br/>5-4 Timing and Control<br/>^5-5 Instruction Cycle<br/>Fetch and Decode<br/>Determine the Type of Instruction<br/>Register-Reference Instructions<br/>5-6 Memory-Reference Instructions<br/>AND to AC<br/>ADD to AC<br/>IDA: Load to AC<br/>STA: Store AC<br/>BUN: Branch Unconditionally<br/>BSA: Branch and Save Return Address<br/>ISZ: Increment and Skip if Zero<br/>Control Flowchart<br/>5-7 Input-Output and Interrupt<br/>Input-Output Configuration<br/>Input-Output Instructions<br/>Program biterrupt<br/>Interrupt Cycle<br/>5-8 Complete Computer Description<br/>5-9 Design of Basic Computer<br/>Control Logic Gates<br/>Control of Registers and Memory<br/>Control of Single Flip-flops<br/>Control of Common Bus<br/>5-10 Design of Accumulator Logic<br/>Control of AC Register<br/>Adder and Logic Circuit<br/>Problems<br/>References<br/>Prograniming the Basic Computer<br/>6-1 Introduction<br/>6-2 Machine Language<br/>6-3 Assembly Language<br/>Rules of the Language<br/>An Example<br/>Translation to Binary<br/>6'4 The Assembler<br/>Representation of Symbolic<br/>Program in Memory<br/>First Pass<br/>Second Pass<br/>6'5 Program Loops<br/>6-6 Programming Arithmetic and Logic Operations<br/>Multiplication Program<br/>Double-Precision Addition<br/>Logic Operations<br/>Shift Operations<br/>6-7 Subroutines<br/>Subroutine Parameters and<br/>Data Linkage<br/>6-8 Input-Output Programming<br/>Character Manipulation<br/>Program Interrupt<br/>Problems<br/>References<br/>Microprogrammed Control<br/>7-1 Control Memory<br/>7-2 Address Sequencing<br/>Conditional Branching<br/>' Mapping of Instruction<br/>Subroutines<br/>7-3 Microprogram Example<br/>Computer Configuration<br/>Microinstruction Format<br/>Symbolic Microinstructions<br/>The Fetch Routine<br/>Symbolic Microprogram<br/>Binary Microprogram<br/>CHAPTER EIQHT<br/>Central Processing Unit<br/>8-1 Introduction<br/>8-2 General Register Organization<br/>Control Word<br/>Exsmplos of Microoperations<br/>8-3 Stack Organization<br/>Register Stack<br/>Memory Stack<br/>Reverse Polish Notation<br/>Evaluation of Arithmetic Expressions<br/>8-4 Instruction Formats<br/>Three-Address Instructions<br/>Two-Address Instructions<br/>One-Address Instructions<br/>Zero-Address Instructions<br/>RISC Instructions<br/>8-5 Addressing Modes<br/>Numerical Example<br/>8-6 E)ata Transfer and Manipulation<br/>Data Transfer Instructions<br/>Data Manipulation Instructions<br/>Arithmetic Instructions<br/>Logical and Bit Manipulation Instructions<br/>Shift Instructions<br/>8-7 Program Control<br/>Status Bit Conditions<br/>Conditional Branch Instructions<br/>Subroutine Call and Return<br/>Program Interrupt<br/>Types of Interrupts —<br/>8-8 Reduced Instruction Set Computer (RISC)<br/>CISC Characteristics<br/>RISC Characteristics<br/>Contents IX<br/>Overlapped Register Windows<br/>Berkeley RISC I<br/>Problems<br/>References<br/>Pipeline and Vector Processing<br/>9-1 Parallel Processing<br/>9-2 Pipelining<br/>General Considerations<br/>9-3 Arithmetic Pipeline<br/>9-4 Instruction Pipeline<br/>Example: Four-Segment Instruction Pipeline<br/>Data Dependency<br/>Handling of Branch Instructions<br/>9-5 RISC Pipeline<br/>Example: Three-Segment Instruction Pipeline<br/>Delayed Load i<br/>Delayed Branch<br/>9,6 Vector Processing<br/>Vector Operations<br/>Matrix MultipUcation<br/>Memory Interleaving<br/>Superscalar Processors<br/>Supercomputers<br/>9-7 Anay Processors<br/>Attached Array Processor<br/>SIMD Array Processor<br/>Problems<br/>References<br/>Computer Arithmetic<br/>10-1 Introduction<br/>10-2 Addition and Subtraction<br/>Addition and Subtraction with<br/>Signed-Magnitude Data<br/>Hardware Implementation<br/>Hardware Algorithm<br/>Addition and Subtraction with<br/>Signed-2's Complement Data<br/>10-3 Multiplication Algorithms<br/>Hardware Implementation for<br/>Signed-Magnitude Data<br/>Hardware Algorithm<br/>Booth Multiplication Algorithm<br/>Array Multiplier<br/>10-4 Division Algorithms<br/>Hardware Implementation for<br/>Signed-Magnitude Data<br/>Divide Overflow<br/>Hardware Algorithm<br/>Other Algorithms<br/>10-5 Floating-Point Arithmetic Operations<br/>Basic Considerations<br/>Register Configuration<br/>Addition and Subtraction<br/>Multiplication<br/>Division<br/>10-6 Decimal Arithmetic Unit<br/>BCD Adder<br/>BCD Subtraction<br/>10-7 Decimal Arithmetic Operations<br/>Addition and Subtraction<br/>Multiplication<br/>Division<br/>Floating-Point Operations<br/>Problems<br/>References<br/>Input-Oulput Organization<br/>11-1 Peripheral Devices ASCII Alphanumeric Characters<br/>11-2 Input-Output Interface<br/>I/O Bus and Interface Modules<br/>I/O versus Memory Bus<br/>Isolated versus Memory-Mapped I/O<br/>Example of I/O Interface<br/>11-3 Asynchronous Data Transfer<br/>Strobe Control<br/>Handshaking<br/>Asynchronous Serial Transfer<br/>Asynchronous Communication Interface<br/>First-In, First-Out Buffer<br/>11-4 Modes of Transfer<br/>Example of Programmed I/O<br/>Interrupt-Initiated I/O<br/>Software Considerations<br/>11-5 Priority Interrupt<br/>Daisy-Chaining Priority<br/>Parcel Priority Interrupt<br/>Priority Encoder<br/>Interrupt Cycle<br/>Software Routines<br/>Initial and Final Operations<br/>11-6 Direct Memory Access (DMA)<br/>DMA Controller<br/>DMA Transfer<br/>11-7 Input-Output Processor (lOP)<br/>CPU-IOP Communication<br/>IBM 370 I/O Channel<br/>Intel 8089 lOP<br/>11-8 Serial Communication<br/>Character-oriented Protocol<br/>Transmission Example<br/>Data Transparency .<br/>Bit-Oriented Protocol<br/>Problems<br/>References<br/>Memory Address Map<br/>Memory Connection to CPU<br/>12-3 Auxiliary Memory<br/>Magnetic Disks<br/>Magnetic Tape<br/>12-4 Associative Memory<br/>Hardware Organization<br/>Match Logic<br/>Read Operation<br/>Write Operation<br/>12-5 Cache Memory<br/>Associative Mapping<br/>Direct Mapping<br/>Set-Associative Mapping<br/>Writing into Cache<br/>Cache Initialization<br/>12-6 Virtual Memory<br/>Address Space and Memory Space<br/>Address Mapping Using Pages<br/>Associative Memory Paee Table<br/>Page Replacement<br/>12-7 Memory Management Hardware<br/>Segmented-Page Mapping<br/>Numerical Example<br/>Memory Protection<br/>Problems<br/>References<br/>Multiprocessors<br/>13-1 Characteristics of Multiprocessors<br/>13-2 Interconnection Structures<br/>Time-Shared Common Bus<br/>Multiport Memory<br/>Crossbar Switch<br/>Multistage Switching Network<br/>Hypercube Interconnection<br/>13-3 Interprocessor Arbitration<br/>System Bus<br/>Serial Arbitration Procedure<br/>Parallel Arbitration Logic<br/>Dynamic Arbitration Algorithms<br/>13-4 Interprocessor Communication<br/>and Synchronization<br/>Interprocessor Synchronization<br/>Mutual Exclusion with a Semaphore<br/>Problems |
| 650 #0 - SUBJECT | |
| Keyword | Computer Architecture. |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | General Books |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Full call number | Accession number | Date last seen | Date last checked out | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Central Library, Sikkim University | Central Library, Sikkim University | General Book Section | 01/06/2016 | 004.22 MAN/C | P33197 | 10/02/2020 | 10/02/2020 | General Books |