Structured computer organization (Record no. 1734)
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000 -LEADER | |
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fixed length control field | 22620nam a2200169 4500 |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
International Standard Book Number | 9788120329133 (pb) |
040 ## - CATALOGING SOURCE | |
Transcribing agency | CUS |
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
Classification number | 004.22 |
Item number | TAN/S |
100 ## - MAIN ENTRY--PERSONAL NAME | |
Personal name | Tanenbaum, Andrew S. |
245 ## - TITLE STATEMENT | |
Title | Structured computer organization |
Statement of responsibility, etc. | Andrew S. Tanenbaum |
250 ## - EDITION STATEMENT | |
Edition statement | 5th ed. |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
Place of publication, distribution, etc. | New Delhi : |
Name of publisher, distributor, etc. | PHI , |
Date of publication, distribution, etc. | 2011. |
300 ## - PHYSICAL DESCRIPTION | |
Extent | xx,777 p. |
Other physical details | ill. ; |
505 ## - FORMATTED CONTENTS NOTE | |
Formatted contents note | 1 INTRODUCTION<br/>1.1 STRUCTURED COMPUTER ORGANIZATION 2<br/>1.1.1 Languages, Levels, and Virtual Machines 2<br/>1.1.2 Contemporary Multilevel Machines 5<br/>1.1.3 Evolution of Multilevel Machines 8<br/>1.2 MILESTONES IN COMPUTER ARCHITECTURE 13<br/>1.2.1 The Zeroth Generation—^Mechanical Computers (1642-1945) 14<br/>1.2.2 The First Generation—Vacuum Tubes (1945-1955) 16<br/>1.2.3 The Second Generation—^Transistors (1955-1965) 19<br/>1.2.4 The Third Generation—Integrated Circuits (1965-1980) 22<br/>1.2.5 The Fourth Generation—^Very Large Scale Integration (1980-?) 23<br/>1.2.6 The Fifth Generation—^Invisible Computers 26<br/>1.3 THE COMPUTER ZOO 27<br/>1.3.1 Technological and Economic Forces 27<br/>1.3.2 The Computer Spectrum 29<br/>1.3.3 Disposable Computers 29<br/>1.3.4 Microcontrollers 31<br/>1.3.5 Game Computers 33<br/>1.3.6 Personal Computers 34<br/>vu<br/>1.3.7 Servers 34<br/>1.3.8 Collections of Workstations 34<br/>1.3.9 Mainframes 36<br/>1.4 EXAMPLE COMPUTER FAMILIES 37<br/>1.4.1 Introduction to the Pentium 4 37<br/>1.4.2 Introduction to the UltraSPARC III 42<br/>1.4.3 Introduction to the 8051 44<br/>1.5 METRIC UNITS 46<br/>1.6 OUTLINE OF THIS BOOK 47<br/>2 COMPUTER SYSTEMS ORGANIZATION<br/>2.1 PROCESSORS 51<br/>2.1.1 CPU Organization 52<br/>2.1.2 Instruction Execution 54<br/>2.1.3 RISC versus CISC 58<br/>2.1.4 Design Principles for Modem Computers 59<br/>2.1.5 Instruction-Level Parallelism 61<br/>2.1.6 Processor-Level Parallelism 65<br/>2.2 PRIMARY MEMORY 69<br/>2.2.1 Bits 69<br/>2.2.2 Memory Addresses 70<br/>2.2.3 Byte Ordering 71<br/>2.2.4 Error-Correcting Codes 73<br/>2.2.5 Cache Memory 77<br/>2.2.6 Memory Packaging and Types 80<br/>2.3 SECONDARY MEMORY 81<br/>2.3.1 Memory Hierarchies 81<br/>2.3.2 Magnetic Disks 82<br/>2.3.3 Floppy Disks 86<br/>2.3.4 IDE Disks 86<br/>2.3.5 SCSI Disks 88<br/>2.3.6 RAID 89<br/>2.3.7 CD-ROMs 93<br/>2.3.8 CD-Recordables 97<br/>2.3.9 CD-Rewritables 99<br/>2.3.10 DVD 99<br/>2.3.11 Blu-Ray 102<br/>2.4 INPUT/OUTPUT 102<br/>2.4.1 Buses 102<br/>2.4.2 Terminals 105<br/>2.4.3 Mice 110<br/>2.4.4 Printers 112<br/>2.4.5 Telecommunications Equipment 117<br/>2.4.6 Digital Cameras 125<br/>2.4.7 Character Codes 127<br/>2.5 SUMMARY 131<br/>3 THE DIGITAL LOGIC LEVEL<br/>3.1 GATES AND BOOLEAN ALGEBRA 135<br/>3.1.1 Gates 136<br/>3.1.2 Boolean Algebra 138<br/>3.1.3 Implementation of Boolean Functions 140<br/>3.1.4 Circuit Equivalence 141<br/>3.2 BASIC DIGITAL LOGIC CIRCUITS 146<br/>3.2.1 Integrated Circuits 146<br/>3.2.2 Combinational Circuits 147<br/>3.2.3 Arithmetic Circuits 152<br/>3.2.4 Clocks 157<br/>3.3 MEMORY 159<br/>3.3.1 Latches 159<br/>3.3.2 Flip-Flops 161<br/>3.3.3 Registers 163<br/>3.3.4 Memory Organization 164<br/>3.3.5 Memory Chips 168<br/>3.3.6 RAMs and ROMs 171<br/>3.4 CPU CHIPS AND BUSES 173<br/>3.4.1 CPU Chips 174<br/>3.4.2 Computer Buses 176<br/>3.4.3 Bus Width 178<br/>3.4.4 Bus Clocking 180<br/>3.4.5 Bus Arbitration 184<br/>3.4.6 Bus Operations 187<br/>3.5 EXAMPLE CPU CHIPS 189<br/>3.5.1 The Pentium 4 189<br/>3.5.2 The UltraSPARC UI 196<br/>3.5.3 The 8051 200<br/>3.6 EXAMPLE BUSES 202<br/>3.6.1 The ISA Bus 203<br/>3.6.2 The PCI Bus 204<br/>3.6.3 PCI Express 212<br/>3.6.4 The Universal Serial Bus 217<br/>3.7 IhJTERFACING 221<br/>3.7.1 I/O Chips 221<br/>3.7.2 Address Decoding 222<br/>3.8 SUMMARY 225<br/>4 THE MICROARCHITECTURE LEVEL<br/>4.1 AN EXAMPLE MICROARCHITECTURE 231<br/>4.1.1 The Data Path 232<br/>4.1.2 Microinstructions 239<br/>4.1.3 Microinstruction Control: The Mic-1 241<br/>4.2 AN EXAMPLE ISA: IJVM 246<br/>4.2.1 Stacks 246<br/>4.2.2 The UVM Memory Model 248<br/>4.2.3 The UVM Instruction Set 250<br/>4.2.4 Compiling Java to IJVM 254<br/>4.3 AN EXAMPLE IMPLEMENTATION 255<br/>4.3.1 Microinstructions and Notation 255<br/>4.3.2 Implementation of UVM Using the Mic-1 260<br/>4.4 DESIGN OF THE MICROARCHITECTURE LEVEL 271<br/>4.4.1 Speed versus Cost 271<br/>4.4.2 Reducing the Execution Path Length 273<br/>4.4.3 A Design with Prefetching: The Mic-2 281<br/>4.4.4 A Pipelined Design: The Mic-3 281<br/>4.4.5 A Seven-Stage Pipeline: The Mic-4 288<br/>4.5 IMPROVING PERFORMANCE 292<br/>4.5.1 Cache Memory 293<br/>4.5.2 Branch Prediction 299<br/>4.5.3 Out-of-Order Execution and Register Renaming 304<br/>4.5.4 Speculative Execution 309<br/>4.6 EXAMPLES OF THE MICROARCHITECTURE LEVEL 311<br/>4.6.1 The Microarchitecture of the Pentium 4 CPU 312<br/>4.6.2 The Microarchitecture of the UltraSPARC-HI Cu CPU 317<br/>4.6.3 The Microarchitecture of the 8051 CPU 323<br/>4.7 COMPARISON OF THE PENTIUM, ULTRASPARC, AND 8051 325<br/>4.8 SUMMARY 326<br/>5 THE INSTRUCTION SET ARCHITECTURE LEVEL 331<br/>5.1 OVERVIEW OF THE ISA LEVEL 333<br/>5.1.1 Properties of the ISA Level 333<br/>5.1.2 Memory Models 335<br/>5.1.3 Registers 337<br/>5.1.4 Instructions 339<br/>5.1.5 Overview of the Pentium 4 ISA Level 339<br/>5.1.6 Overview of the UltraSPARC III ISA Level 341<br/>5.1.7 Overview of the 8051 ISA Level 345<br/>5.2 DATATYPES 348<br/>5.2.1 Numeric Data Types 348<br/>5.2.2 Nonnumeric Data Types 349<br/>5.2.3 Data Types on the Pentium 4 350<br/>5.2.4 Data Types on the UltraSPARC III 350<br/>5.2.5 Data Types on the 8051 351<br/>5.3 INSTRUCTION FORMATS 351<br/>5.3.1 Design Criteria for Instruction Formats 352<br/>5.3.2 Expanding Opcodes 354<br/>5.3.3 The Pentium 4 Instruction Formats 357<br/>5.3.4 The UltraSPARC ni Instruction Formats 358<br/>5.3.5 The 8051 Instruction Formats 359<br/>5.4 ADDRESSING 360<br/>5.4.1 Addressing Modes 360<br/>5.4.2 Immediate Addressing 361<br/>5.4.3 Direct Addressing 361<br/>5.4.4 Register Addressing 361<br/>5.4.5 Register Indirect Addressing 362<br/>5.4.6 Indexed Addressing 363<br/>5.4.7 Based-Indexed Addressing 365<br/>5.4.8 Stack Addressing 365<br/>5.4.9 Addressing Modes for Branch Instructions 369<br/>5.4.10 Orthogonality of Opcodes and Addressing Modes 369<br/>5.4.11 The Pentium 4 Addressing Modes 371<br/>5.4.12 The UltraSPARC III Addressing Modes 373<br/>5.4.13 The 8051 Addressing Modes 373<br/>5.4.14 Discussion of Addressing Modes 374<br/>5.5 INSTRUCTION TYPES 375<br/>5.5.1 Data Movement Instructions 375<br/>5.5.2 Dyadic Operations 376<br/>5.5.3 Monadic Operations 377<br/>5.5.4 Comparisons and Conditional Branches 379<br/>5.5.5 Procedure Call Instructions 381<br/>5.5.6 Loop Control 382<br/>5.5.7 Input/Output 383<br/>5.5.8 The Pentium 4 Instructions 386<br/>5.5.9 The UltraSPARC III Instructions 389<br/>5.5.10 The 8051 Instructions 392<br/>5.5.11 Comparison of Instruction Sets 392<br/>5.6 FLOW OF CONTROL 395<br/>5.6.1 Sequential Flow of Control and Branches 395<br/>5.6.2 Procedures 396<br/>5.6.3 Coroutines 401<br/>5.6.5 Traps 404<br/>5.6.5 Interrupts 404<br/>5.7 A DETAILED EXAMPLE: THE TOWERS OF HANOI 408<br/>5.7.1 The Towers of Hanoi in Pentium 4 Assembly Language 409<br/>5.7.2 The Towers of Hanoi in UltraSPARC III Assembly Language 409<br/>5.8 THE IA-64 ARCHITECTURE AND THE ITANIUM 2 411<br/>5.8.1 The Problem with the Pentium 4 413<br/>5.8.2 The IA-64 Model: Explicitly Parallel Instruction Computing 414<br/>5.8.3 Reducing Memory References 415<br/>5.8.4 Instruction Scheduling 416<br/>5.8.5 Reducing Conditional Branches: Predication 418<br/>5.8.6 Speculative Loads 420<br/>5.9 SUMMARY 421<br/>6 THE OPERATING SYSTEM MACHINE LEVEL<br/>6.1 VIRTUAL MEMORY 428<br/>6.1.1 Paging 429<br/>6.1.2 Implementation of Paging 431<br/>6.1.3 Demand Paging and the Working Set Model 433<br/>6.1.4 Page Replacement Policy 436<br/>6.1.5 Page Size and Fragmentation 438<br/>6.1.6 Segmentation 439<br/>6.1.7 Implementation of Segmentation 442<br/>6.1.8 Virtual Memory on the Pentium 4 445<br/>6.1.9 Virtual Memory on the UltraSPARC m 450<br/>6.1.10 Virtual Memory and Caching 452<br/>6.2 VIRTUAL I/O INSTRUCTIONS 453<br/>6.2.1 Files 454<br/>6.2.2 Implementation of Virtual I/O Instructions 455<br/>6.2.3 Directory Management Instructions 459<br/>6.3 VIRTUAL INSTRUCTIONS FOR PARALLEL PROCESSING 460<br/>6.3.1 Process Creation 461<br/>6.3.2 Race Conditions 462<br/>6.3.3 Process Synchronization Using Semaphores 466<br/>6.4 EXAMPLE OPERATING SYSTEMS 470<br/>6.4.1 Introduction 470<br/>6.4.2 Examples of Virtual Memory 479<br/>6.4.3 Examples of Virtual I/O 482<br/>6.4.4 Examples of Process Management 493<br/>7 THE ASSEMBLY LANGUAGE LEVEL<br/>7.1 INTRODUCTION TO ASSEMBLY LANGUAGE 508<br/>7.1.1 What Is an Assembly Language? 508<br/>7.1.2 Why Use Assembly Language? 509<br/>7.1.3 Format of an Assembly Language Statement 512<br/>7.1.4 Pseudoinstructions 515<br/>7.2 MACROS 517<br/>7.2.1 Macro Definition, Call, and Expansion 518<br/>7.2.2 Macros with Parameters 520<br/>7.2.3 Advanced Features 521<br/>7.2.4 Implementation of a Macro Facility in an Assembler 521<br/>7.3 THE ASSEMBLY PROCESS 522<br/>7.3.1 Two-Pass Assemblers 522<br/>7.3.2 Pass One 523<br/>7.3.3 Pass Two 527<br/>7.3.4 The Symbol Table 529<br/>7.4 LINKING AND LOADING 530<br/>7.4.1 Tasks Performed by the Linker 532<br/>7.4.2 Structure of an Object Module 535<br/>7.4.3 Binding Time and Dynamic Relocation 536<br/>7.4.4 Dynamic Linking 539<br/>8 PARALLEL COMPUTER ARCHITECTURES<br/>8.1 ON-CHIP PARALELLISM 548<br/>8.1.1 Instruction-Level Parallelism 549<br/>8.1.2 On-Chip Multithreading 556<br/>8.1.3 Single-Chip Multiprocessors 562<br/>8.2 COPROCESSORS 567<br/>8.2.1 Network Processors 568<br/>8.2.2 Media Processors 576<br/>8.2.3 Cryptoprocessors 581<br/>8.3 SHARED-MEMORY MULTIPROCESSORS 582<br/>8.3.1 Multiprocessors vs. Multicomputers 582<br/>8.3.2 Memory Semantics 590<br/>8.3.3 UMA Symmetric Multiprocessor Architectures 594<br/>8.3.4 NUMA Multiprocessors 602<br/>8.3.5 COMA Multiprocessors 611<br/>8.4 MESSAGE-PASSING MULTICOMPUTERS 612<br/>8.4.1 Interconnection Networks 614<br/>8.4.2 MPPs—Massively Parallel Processors 617<br/>8.4.3 Cluster Computing 627<br/>8.4.4 Communication Software for Multicomputers 632<br/>8.4.5 Scheduling 635<br/>8.4.6 Application-Level Shared Memory 636<br/>8.4.7 Performance 643<br/>8.5 GRID COMPUTING 649<br/>9 READING LIST AND BIBLIOGRAPHY<br/>9.1 SUGGESTIONS FOR FURTHER READING 655<br/>9.1.1 Introduction and General Works 655<br/>9.1.2 Computer Systems Organization 657<br/>9.1.3 The Digital Logic Level 658<br/>9.1.4 The Microarchitecture Level 659<br/>9.1.5 The Instruction Set Architecture Level 659<br/>9.1.6 The Operatiiig System Machine Level 660<br/>9.1.7 The Assembly Language Level 661<br/>9.1.8 Parallel Computer Architectures 661<br/>9.1.9 Binary and Floating-Point Numbers 663<br/>9.1.10 Assembly Language Progranuning 664<br/>9.2 ALPHABETICAL BIBLIOGRAPHY 664<br/>A BINARY NUMBERS<br/>A.1 FINnE-PRECISIGN NUMBERS 679<br/>A.2 RADIX NUMBER SYSTEMS 681<br/>A.3 CONVERSION FROM ONE RADIX TO ANOTHER 683<br/>A.4 NEGATIVE BINARY NUMBERS 685<br/>A.5 BINARY ARITHMETIC 688<br/>B FLOATING-POINT NUMBERS<br/>B.l PRINCIPLES OF FLOATING POINT 692<br/>B.2 IEEE FLOATING-POINT STANDARD 754 694<br/>C ASSEMBLY LANGUAGE PROGRAMMING<br/>C.l OVERVIEW 702<br/>C.1.1 Assembly Language 702<br/>C.l.2 A Small Assembly Language Program 703<br/>C.2 THE 8088 PROCESSOR 704<br/>C.2.1 The Processor Cycle 705<br/>C.2,2 The General Registers 705<br/>C.2.3 Pointer Registers 708<br/>C.3 MEMORY AND ADDRESSING 709<br/>C.3.1 Memory Organization and Segments 709<br/>C.3.2 Addressing 711<br/>C.4 THE 8088 INSTRUCTION SET 715<br/>C.4.1 Move, Copy and Arithmetic 715<br/>C.4.2 Logical, Bit and Shift Operations 718<br/>C.4.3 Loop and Repetitive String Operations 718<br/>C.4.4 Jump and Call Instructions 719<br/>C.4.5 Subroutine Calls 721<br/>C.4.6 System Calls and System Subroutines 723<br/>C.4.7 Final Remarks on the Instruction Set 725<br/>C.5 THE ASSEMBLER 725<br/>C.5.1 Introduction 726<br/>C.5.2 The ACK-Based Tutorial Assembler as88 727<br/>C.5.3 Some Differences with Other 8088 Assemblers 730<br/>C.6 THE TRACER 732<br/>C.6.1 Tracer Commands 734<br/>C.7 GETTING STARTED 735<br/>C.8 EXAMPLES 736<br/>C.8.1 Hello World Example 736<br/>C.8.2 General Registers Example 740<br/>C.8.3 Call Command and Pointer Registers 742<br/>C.8.4 Debugging an Array Print Program 744<br/>C.8.5 String Manipulation and String Instructions 748<br/>C.8.6 Dispatch Tables 750<br/>C.8.7 Buffered and Random File Access 7521 INTRODUCTION<br/>1.1 STRUCTURED COMPUTER ORGANIZATION 2<br/>1.1.1 Languages, Levels, and Virtual Machines 2<br/>1.1.2 Contemporary Multilevel Machines 5<br/>1.1.3 Evolution of Multilevel Machines 8<br/>1.2 MILESTONES IN COMPUTER ARCHITECTURE 13<br/>1.2.1 The Zeroth Generation—^Mechanical Computers (1642-1945) 14<br/>1.2.2 The First Generation—Vacuum Tubes (1945-1955) 16<br/>1.2.3 The Second Generation—^Transistors (1955-1965) 19<br/>1.2.4 The Third Generation—Integrated Circuits (1965-1980) 22<br/>1.2.5 The Fourth Generation—^Very Large Scale Integration (1980-?) 23<br/>1.2.6 The Fifth Generation—^Invisible Computers 26<br/>1.3 THE COMPUTER ZOO 27<br/>1.3.1 Technological and Economic Forces 27<br/>1.3.2 The Computer Spectrum 29<br/>1.3.3 Disposable Computers 29<br/>1.3.4 Microcontrollers 31<br/>1.3.5 Game Computers 33<br/>1.3.6 Personal Computers 34<br/>vu<br/>1.3.7 Servers 34<br/>1.3.8 Collections of Workstations 34<br/>1.3.9 Mainframes 36<br/>1.4 EXAMPLE COMPUTER FAMILIES 37<br/>1.4.1 Introduction to the Pentium 4 37<br/>1.4.2 Introduction to the UltraSPARC III 42<br/>1.4.3 Introduction to the 8051 44<br/>1.5 METRIC UNITS 46<br/>1.6 OUTLINE OF THIS BOOK 47<br/>2 COMPUTER SYSTEMS ORGANIZATION<br/>2.1 PROCESSORS 51<br/>2.1.1 CPU Organization 52<br/>2.1.2 Instruction Execution 54<br/>2.1.3 RISC versus CISC 58<br/>2.1.4 Design Principles for Modem Computers 59<br/>2.1.5 Instruction-Level Parallelism 61<br/>2.1.6 Processor-Level Parallelism 65<br/>2.2 PRIMARY MEMORY 69<br/>2.2.1 Bits 69<br/>2.2.2 Memory Addresses 70<br/>2.2.3 Byte Ordering 71<br/>2.2.4 Error-Correcting Codes 73<br/>2.2.5 Cache Memory 77<br/>2.2.6 Memory Packaging and Types 80<br/>2.3 SECONDARY MEMORY 81<br/>2.3.1 Memory Hierarchies 81<br/>2.3.2 Magnetic Disks 82<br/>2.3.3 Floppy Disks 86<br/>2.3.4 IDE Disks 86<br/>2.3.5 SCSI Disks 88<br/>2.3.6 RAID 89<br/>2.3.7 CD-ROMs 93<br/>2.3.8 CD-Recordables 97<br/>2.3.9 CD-Rewritables 99<br/>2.3.10 DVD 99<br/>2.3.11 Blu-Ray 102<br/>2.4 INPUT/OUTPUT 102<br/>2.4.1 Buses 102<br/>2.4.2 Terminals 105<br/>2.4.3 Mice 110<br/>2.4.4 Printers 112<br/>2.4.5 Telecommunications Equipment 117<br/>2.4.6 Digital Cameras 125<br/>2.4.7 Character Codes 127<br/>2.5 SUMMARY 131<br/>3 THE DIGITAL LOGIC LEVEL<br/>3.1 GATES AND BOOLEAN ALGEBRA 135<br/>3.1.1 Gates 136<br/>3.1.2 Boolean Algebra 138<br/>3.1.3 Implementation of Boolean Functions 140<br/>3.1.4 Circuit Equivalence 141<br/>3.2 BASIC DIGITAL LOGIC CIRCUITS 146<br/>3.2.1 Integrated Circuits 146<br/>3.2.2 Combinational Circuits 147<br/>3.2.3 Arithmetic Circuits 152<br/>3.2.4 Clocks 157<br/>3.3 MEMORY 159<br/>3.3.1 Latches 159<br/>3.3.2 Flip-Flops 161<br/>3.3.3 Registers 163<br/>3.3.4 Memory Organization 164<br/>3.3.5 Memory Chips 168<br/>3.3.6 RAMs and ROMs 171<br/>3.4 CPU CHIPS AND BUSES 173<br/>3.4.1 CPU Chips 174<br/>3.4.2 Computer Buses 176<br/>3.4.3 Bus Width 178<br/>3.4.4 Bus Clocking 180<br/>3.4.5 Bus Arbitration 184<br/>3.4.6 Bus Operations 187<br/>3.5 EXAMPLE CPU CHIPS 189<br/>3.5.1 The Pentium 4 189<br/>3.5.2 The UltraSPARC UI 196<br/>3.5.3 The 8051 200<br/>3.6 EXAMPLE BUSES 202<br/>3.6.1 The ISA Bus 203<br/>3.6.2 The PCI Bus 204<br/>3.6.3 PCI Express 212<br/>3.6.4 The Universal Serial Bus 217<br/>3.7 IhJTERFACING 221<br/>3.7.1 I/O Chips 221<br/>3.7.2 Address Decoding 222<br/>3.8 SUMMARY 225<br/>4 THE MICROARCHITECTURE LEVEL<br/>4.1 AN EXAMPLE MICROARCHITECTURE 231<br/>4.1.1 The Data Path 232<br/>4.1.2 Microinstructions 239<br/>4.1.3 Microinstruction Control: The Mic-1 241<br/>4.2 AN EXAMPLE ISA: IJVM 246<br/>4.2.1 Stacks 246<br/>4.2.2 The UVM Memory Model 248<br/>4.2.3 The UVM Instruction Set 250<br/>4.2.4 Compiling Java to IJVM 254<br/>4.3 AN EXAMPLE IMPLEMENTATION 255<br/>4.3.1 Microinstructions and Notation 255<br/>4.3.2 Implementation of UVM Using the Mic-1 260<br/>4.4 DESIGN OF THE MICROARCHITECTURE LEVEL 271<br/>4.4.1 Speed versus Cost 271<br/>4.4.2 Reducing the Execution Path Length 273<br/>4.4.3 A Design with Prefetching: The Mic-2 281<br/>4.4.4 A Pipelined Design: The Mic-3 281<br/>4.4.5 A Seven-Stage Pipeline: The Mic-4 288<br/>4.5 IMPROVING PERFORMANCE 292<br/>4.5.1 Cache Memory 293<br/>4.5.2 Branch Prediction 299<br/>4.5.3 Out-of-Order Execution and Register Renaming 304<br/>4.5.4 Speculative Execution 309<br/>4.6 EXAMPLES OF THE MICROARCHITECTURE LEVEL 311<br/>4.6.1 The Microarchitecture of the Pentium 4 CPU 312<br/>4.6.2 The Microarchitecture of the UltraSPARC-HI Cu CPU 317<br/>4.6.3 The Microarchitecture of the 8051 CPU 323<br/>4.7 COMPARISON OF THE PENTIUM, ULTRASPARC, AND 8051 325<br/>4.8 SUMMARY 326<br/>5 THE INSTRUCTION SET ARCHITECTURE LEVEL 331<br/>5.1 OVERVIEW OF THE ISA LEVEL 333<br/>5.1.1 Properties of the ISA Level 333<br/>5.1.2 Memory Models 335<br/>5.1.3 Registers 337<br/>5.1.4 Instructions 339<br/>5.1.5 Overview of the Pentium 4 ISA Level 339<br/>5.1.6 Overview of the UltraSPARC III ISA Level 341<br/>5.1.7 Overview of the 8051 ISA Level 345<br/>5.2 DATATYPES 348<br/>5.2.1 Numeric Data Types 348<br/>5.2.2 Nonnumeric Data Types 349<br/>5.2.3 Data Types on the Pentium 4 350<br/>5.2.4 Data Types on the UltraSPARC III 350<br/>5.2.5 Data Types on the 8051 351<br/>5.3 INSTRUCTION FORMATS 351<br/>5.3.1 Design Criteria for Instruction Formats 352<br/>5.3.2 Expanding Opcodes 354<br/>5.3.3 The Pentium 4 Instruction Formats 357<br/>5.3.4 The UltraSPARC ni Instruction Formats 358<br/>5.3.5 The 8051 Instruction Formats 359<br/>5.4 ADDRESSING 360<br/>5.4.1 Addressing Modes 360<br/>5.4.2 Immediate Addressing 361<br/>5.4.3 Direct Addressing 361<br/>5.4.4 Register Addressing 361<br/>5.4.5 Register Indirect Addressing 362<br/>5.4.6 Indexed Addressing 363<br/>5.4.7 Based-Indexed Addressing 365<br/>5.4.8 Stack Addressing 365<br/>5.4.9 Addressing Modes for Branch Instructions 369<br/>5.4.10 Orthogonality of Opcodes and Addressing Modes 369<br/>5.4.11 The Pentium 4 Addressing Modes 371<br/>5.4.12 The UltraSPARC III Addressing Modes 373<br/>5.4.13 The 8051 Addressing Modes 373<br/>5.4.14 Discussion of Addressing Modes 374<br/>5.5 INSTRUCTION TYPES 375<br/>5.5.1 Data Movement Instructions 375<br/>5.5.2 Dyadic Operations 376<br/>5.5.3 Monadic Operations 377<br/>5.5.4 Comparisons and Conditional Branches 379<br/>5.5.5 Procedure Call Instructions 381<br/>5.5.6 Loop Control 382<br/>5.5.7 Input/Output 383<br/>5.5.8 The Pentium 4 Instructions 386<br/>5.5.9 The UltraSPARC III Instructions 389<br/>5.5.10 The 8051 Instructions 392<br/>5.5.11 Comparison of Instruction Sets 392<br/>5.6 FLOW OF CONTROL 395<br/>5.6.1 Sequential Flow of Control and Branches 395<br/>5.6.2 Procedures 396<br/>5.6.3 Coroutines 401<br/>5.6.5 Traps 404<br/>5.6.5 Interrupts 404<br/>5.7 A DETAILED EXAMPLE: THE TOWERS OF HANOI 408<br/>5.7.1 The Towers of Hanoi in Pentium 4 Assembly Language 409<br/>5.7.2 The Towers of Hanoi in UltraSPARC III Assembly Language 409<br/>5.8 THE IA-64 ARCHITECTURE AND THE ITANIUM 2 411<br/>5.8.1 The Problem with the Pentium 4 413<br/>5.8.2 The IA-64 Model: Explicitly Parallel Instruction Computing 414<br/>5.8.3 Reducing Memory References 415<br/>5.8.4 Instruction Scheduling 416<br/>5.8.5 Reducing Conditional Branches: Predication 418<br/>5.8.6 Speculative Loads 420<br/>5.9 SUMMARY 421<br/>6 THE OPERATING SYSTEM MACHINE LEVEL<br/>6.1 VIRTUAL MEMORY 428<br/>6.1.1 Paging 429<br/>6.1.2 Implementation of Paging 431<br/>6.1.3 Demand Paging and the Working Set Model 433<br/>6.1.4 Page Replacement Policy 436<br/>6.1.5 Page Size and Fragmentation 438<br/>6.1.6 Segmentation 439<br/>6.1.7 Implementation of Segmentation 442<br/>6.1.8 Virtual Memory on the Pentium 4 445<br/>6.1.9 Virtual Memory on the UltraSPARC m 450<br/>6.1.10 Virtual Memory and Caching 452<br/>6.2 VIRTUAL I/O INSTRUCTIONS 453<br/>6.2.1 Files 454<br/>6.2.2 Implementation of Virtual I/O Instructions 455<br/>6.2.3 Directory Management Instructions 459<br/>6.3 VIRTUAL INSTRUCTIONS FOR PARALLEL PROCESSING 460<br/>6.3.1 Process Creation 461<br/>6.3.2 Race Conditions 462<br/>6.3.3 Process Synchronization Using Semaphores 466<br/>6.4 EXAMPLE OPERATING SYSTEMS 470<br/>6.4.1 Introduction 470<br/>6.4.2 Examples of Virtual Memory 479<br/>6.4.3 Examples of Virtual I/O 482<br/>6.4.4 Examples of Process Management 493<br/>7 THE ASSEMBLY LANGUAGE LEVEL<br/>7.1 INTRODUCTION TO ASSEMBLY LANGUAGE 508<br/>7.1.1 What Is an Assembly Language? 508<br/>7.1.2 Why Use Assembly Language? 509<br/>7.1.3 Format of an Assembly Language Statement 512<br/>7.1.4 Pseudoinstructions 515<br/>7.2 MACROS 517<br/>7.2.1 Macro Definition, Call, and Expansion 518<br/>7.2.2 Macros with Parameters 520<br/>7.2.3 Advanced Features 521<br/>7.2.4 Implementation of a Macro Facility in an Assembler 521<br/>7.3 THE ASSEMBLY PROCESS 522<br/>7.3.1 Two-Pass Assemblers 522<br/>7.3.2 Pass One 523<br/>7.3.3 Pass Two 527<br/>7.3.4 The Symbol Table 529<br/>7.4 LINKING AND LOADING 530<br/>7.4.1 Tasks Performed by the Linker 532<br/>7.4.2 Structure of an Object Module 535<br/>7.4.3 Binding Time and Dynamic Relocation 536<br/>7.4.4 Dynamic Linking 539<br/>8 PARALLEL COMPUTER ARCHITECTURES<br/>8.1 ON-CHIP PARALELLISM 548<br/>8.1.1 Instruction-Level Parallelism 549<br/>8.1.2 On-Chip Multithreading 556<br/>8.1.3 Single-Chip Multiprocessors 562<br/>8.2 COPROCESSORS 567<br/>8.2.1 Network Processors 568<br/>8.2.2 Media Processors 576<br/>8.2.3 Cryptoprocessors 581<br/>8.3 SHARED-MEMORY MULTIPROCESSORS 582<br/>8.3.1 Multiprocessors vs. Multicomputers 582<br/>8.3.2 Memory Semantics 590<br/>8.3.3 UMA Symmetric Multiprocessor Architectures 594<br/>8.3.4 NUMA Multiprocessors 602<br/>8.3.5 COMA Multiprocessors 611<br/>8.4 MESSAGE-PASSING MULTICOMPUTERS 612<br/>8.4.1 Interconnection Networks 614<br/>8.4.2 MPPs—Massively Parallel Processors 617<br/>8.4.3 Cluster Computing 627<br/>8.4.4 Communication Software for Multicomputers 632<br/>8.4.5 Scheduling 635<br/>8.4.6 Application-Level Shared Memory 636<br/>8.4.7 Performance 643<br/>8.5 GRID COMPUTING 649<br/>9 READING LIST AND BIBLIOGRAPHY<br/>9.1 SUGGESTIONS FOR FURTHER READING 655<br/>9.1.1 Introduction and General Works 655<br/>9.1.2 Computer Systems Organization 657<br/>9.1.3 The Digital Logic Level 658<br/>9.1.4 The Microarchitecture Level 659<br/>9.1.5 The Instruction Set Architecture Level 659<br/>9.1.6 The Operatiiig System Machine Level 660<br/>9.1.7 The Assembly Language Level 661<br/>9.1.8 Parallel Computer Architectures 661<br/>9.1.9 Binary and Floating-Point Numbers 663<br/>9.1.10 Assembly Language Progranuning 664<br/>9.2 ALPHABETICAL BIBLIOGRAPHY 664<br/>A BINARY NUMBERS<br/>A.1 FINnE-PRECISIGN NUMBERS 679<br/>A.2 RADIX NUMBER SYSTEMS 681<br/>A.3 CONVERSION FROM ONE RADIX TO ANOTHER 683<br/>A.4 NEGATIVE BINARY NUMBERS 685<br/>A.5 BINARY ARITHMETIC 688<br/>B FLOATING-POINT NUMBERS<br/>B.l PRINCIPLES OF FLOATING POINT 692<br/>B.2 IEEE FLOATING-POINT STANDARD 754 694<br/>C ASSEMBLY LANGUAGE PROGRAMMING<br/>C.l OVERVIEW 702<br/>C.1.1 Assembly Language 702<br/>C.l.2 A Small Assembly Language Program 703<br/>C.2 THE 8088 PROCESSOR 704<br/>C.2.1 The Processor Cycle 705<br/>C.2,2 The General Registers 705<br/>C.2.3 Pointer Registers 708<br/>C.3 MEMORY AND ADDRESSING 709<br/>C.3.1 Memory Organization and Segments 709<br/>C.3.2 Addressing 711<br/>C.4 THE 8088 INSTRUCTION SET 715<br/>C.4.1 Move, Copy and Arithmetic 715<br/>C.4.2 Logical, Bit and Shift Operations 718<br/>C.4.3 Loop and Repetitive String Operations 718<br/>C.4.4 Jump and Call Instructions 719<br/>C.4.5 Subroutine Calls 721<br/>C.4.6 System Calls and System Subroutines 723<br/>C.4.7 Final Remarks on the Instruction Set 725<br/>C.5 THE ASSEMBLER 725<br/>C.5.1 Introduction 726<br/>C.5.2 The ACK-Based Tutorial Assembler as88 727<br/>C.5.3 Some Differences with Other 8088 Assemblers 730<br/>C.6 THE TRACER 732<br/>C.6.1 Tracer Commands 734<br/>C.7 GETTING STARTED 735<br/>C.8 EXAMPLES 736<br/>C.8.1 Hello World Example 736<br/>C.8.2 General Registers Example 740<br/>C.8.3 Call Command and Pointer Registers 742<br/>C.8.4 Debugging an Array Print Program 744<br/>C.8.5 String Manipulation and String Instructions 748<br/>C.8.6 Dispatch Tables 750<br/>C.8.7 Buffered and Random File Access 752 |
650 ## - SUBJECT | |
Keyword | Computer Organization |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Koha item type | General Books |
Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Full call number | Accession number | Date last seen | Date last checked out | Koha item type |
---|---|---|---|---|---|---|---|---|---|---|---|---|
Central Library, Sikkim University | Central Library, Sikkim University | General Book Section | 31/05/2016 | 004.22 TAN/S | P18880 | 14/07/2018 | 14/07/2018 | General Books |