Computer system architecture /
Mano, M. Morris,
Computer system architecture / M. Morris Mano. - 2nd ed. - Englewood Cliffs, N.J. : Prentice-Hall, 2007 p. - xii, 520 p.ill.: 25 cm.
Digital Logic Circuits
1-1 Digital Computers
1-2 Logic Gates
1-3 Boolean Algebra
Complement of a Function
1-4 Map Simplification
Product-of-Sums Simplification
Don't-Care Conditions
1-5 Combinational Circuits
Half-Adder
Full-Adder
1-6 Flip-Flops
SR Flip-Flop
D Flip-Flop
JK Flip-Flop
T Flip-Flop
Edge-Triggered Flip-Flops
Excitation Tables
1-7 Sequential Circuits
Flip-Flop Input Equations
State Table
State Diagram
Design Example
Design Procedure
Problems
References
Digital Components
2-1 Integrated Circuits
2-2 Decoders
NAND Gate Decoder
Decoder Expansion
Encoders
2-3 Multiplexers
2-4 Registers
Register with Parallel Load
2-5 Shift Registers
Bidirectional Shift Register with Parallel Load
2-6 Binary Counters
Binary Counter with Parallel Load
2-7 Memory Unit
Random-Access Memory
Read-Only Memory
Types of ROMs
Problems
References
Data Representation
3-1 Data Types
Number Systems
Octal and Hexadecimal Numbers
Decimal Representation
Alphanumeric Representation
3-2 Complements
(r — l)'s Complement
(Ps) Complement
Subtraction of Unsigned Numbers
3-3 Fixed-Point Representation
Integer Representation
Aiidunetic Addition
Arithmetic Subtraction
Overflow t
Decimal Fixed-Point Representation
3-4 Floating-Point Representation
3 "5 Other Binary Codes
Gray Code
Other Decimal Codes
Other Alphanumeric Codes
3 "6 Error Detection Codes
Problems
Register Transfer and Microoperations
4" 1 Register Transfer Language
4'2 Register Transfer
4'3 Bus and Memory Transfers
Three-State Bus Buffers
Memory Transfer
4'4 Arithmetic Microoperations
Binary Adder
Binary Adder-Subtractor
Binary Incrementer
Arithmetic Circuit
4'5 Logic Microoperations
List of Logic Microoperations
Hardware Implementation
Some Apphcations
4-6 Shift Microoperations
Hardware Implementation
4-7 Arithmetic Logic Shift Unit
4'8 Hardware Description Languages
Introduction to VHDL
Basic Framework and Syntax
Problems
Basic Computer Organization and Design
5-1 Instruction Codes
Stored Program Organization
Indirect Address
5 "2 Computer Registers
Common Bus System
5'3 Computer Instructions
Instruction Set Completeness
5-4 Timing and Control
^5-5 Instruction Cycle
Fetch and Decode
Determine the Type of Instruction
Register-Reference Instructions
5-6 Memory-Reference Instructions
AND to AC
ADD to AC
IDA: Load to AC
STA: Store AC
BUN: Branch Unconditionally
BSA: Branch and Save Return Address
ISZ: Increment and Skip if Zero
Control Flowchart
5-7 Input-Output and Interrupt
Input-Output Configuration
Input-Output Instructions
Program biterrupt
Interrupt Cycle
5-8 Complete Computer Description
5-9 Design of Basic Computer
Control Logic Gates
Control of Registers and Memory
Control of Single Flip-flops
Control of Common Bus
5-10 Design of Accumulator Logic
Control of AC Register
Adder and Logic Circuit
Problems
References
Prograniming the Basic Computer
6-1 Introduction
6-2 Machine Language
6-3 Assembly Language
Rules of the Language
An Example
Translation to Binary
6'4 The Assembler
Representation of Symbolic
Program in Memory
First Pass
Second Pass
6'5 Program Loops
6-6 Programming Arithmetic and Logic Operations
Multiplication Program
Double-Precision Addition
Logic Operations
Shift Operations
6-7 Subroutines
Subroutine Parameters and
Data Linkage
6-8 Input-Output Programming
Character Manipulation
Program Interrupt
Problems
References
Microprogrammed Control
7-1 Control Memory
7-2 Address Sequencing
Conditional Branching
' Mapping of Instruction
Subroutines
7-3 Microprogram Example
Computer Configuration
Microinstruction Format
Symbolic Microinstructions
The Fetch Routine
Symbolic Microprogram
Binary Microprogram
CHAPTER EIQHT
Central Processing Unit
8-1 Introduction
8-2 General Register Organization
Control Word
Exsmplos of Microoperations
8-3 Stack Organization
Register Stack
Memory Stack
Reverse Polish Notation
Evaluation of Arithmetic Expressions
8-4 Instruction Formats
Three-Address Instructions
Two-Address Instructions
One-Address Instructions
Zero-Address Instructions
RISC Instructions
8-5 Addressing Modes
Numerical Example
8-6 E)ata Transfer and Manipulation
Data Transfer Instructions
Data Manipulation Instructions
Arithmetic Instructions
Logical and Bit Manipulation Instructions
Shift Instructions
8-7 Program Control
Status Bit Conditions
Conditional Branch Instructions
Subroutine Call and Return
Program Interrupt
Types of Interrupts —
8-8 Reduced Instruction Set Computer (RISC)
CISC Characteristics
RISC Characteristics
Contents IX
Overlapped Register Windows
Berkeley RISC I
Problems
References
Pipeline and Vector Processing
9-1 Parallel Processing
9-2 Pipelining
General Considerations
9-3 Arithmetic Pipeline
9-4 Instruction Pipeline
Example: Four-Segment Instruction Pipeline
Data Dependency
Handling of Branch Instructions
9-5 RISC Pipeline
Example: Three-Segment Instruction Pipeline
Delayed Load i
Delayed Branch
9,6 Vector Processing
Vector Operations
Matrix MultipUcation
Memory Interleaving
Superscalar Processors
Supercomputers
9-7 Anay Processors
Attached Array Processor
SIMD Array Processor
Problems
References
Computer Arithmetic
10-1 Introduction
10-2 Addition and Subtraction
Addition and Subtraction with
Signed-Magnitude Data
Hardware Implementation
Hardware Algorithm
Addition and Subtraction with
Signed-2's Complement Data
10-3 Multiplication Algorithms
Hardware Implementation for
Signed-Magnitude Data
Hardware Algorithm
Booth Multiplication Algorithm
Array Multiplier
10-4 Division Algorithms
Hardware Implementation for
Signed-Magnitude Data
Divide Overflow
Hardware Algorithm
Other Algorithms
10-5 Floating-Point Arithmetic Operations
Basic Considerations
Register Configuration
Addition and Subtraction
Multiplication
Division
10-6 Decimal Arithmetic Unit
BCD Adder
BCD Subtraction
10-7 Decimal Arithmetic Operations
Addition and Subtraction
Multiplication
Division
Floating-Point Operations
Problems
References
Input-Oulput Organization
11-1 Peripheral Devices ASCII Alphanumeric Characters
11-2 Input-Output Interface
I/O Bus and Interface Modules
I/O versus Memory Bus
Isolated versus Memory-Mapped I/O
Example of I/O Interface
11-3 Asynchronous Data Transfer
Strobe Control
Handshaking
Asynchronous Serial Transfer
Asynchronous Communication Interface
First-In, First-Out Buffer
11-4 Modes of Transfer
Example of Programmed I/O
Interrupt-Initiated I/O
Software Considerations
11-5 Priority Interrupt
Daisy-Chaining Priority
Parcel Priority Interrupt
Priority Encoder
Interrupt Cycle
Software Routines
Initial and Final Operations
11-6 Direct Memory Access (DMA)
DMA Controller
DMA Transfer
11-7 Input-Output Processor (lOP)
CPU-IOP Communication
IBM 370 I/O Channel
Intel 8089 lOP
11-8 Serial Communication
Character-oriented Protocol
Transmission Example
Data Transparency .
Bit-Oriented Protocol
Problems
References
Memory Address Map
Memory Connection to CPU
12-3 Auxiliary Memory
Magnetic Disks
Magnetic Tape
12-4 Associative Memory
Hardware Organization
Match Logic
Read Operation
Write Operation
12-5 Cache Memory
Associative Mapping
Direct Mapping
Set-Associative Mapping
Writing into Cache
Cache Initialization
12-6 Virtual Memory
Address Space and Memory Space
Address Mapping Using Pages
Associative Memory Paee Table
Page Replacement
12-7 Memory Management Hardware
Segmented-Page Mapping
Numerical Example
Memory Protection
Problems
References
Multiprocessors
13-1 Characteristics of Multiprocessors
13-2 Interconnection Structures
Time-Shared Common Bus
Multiport Memory
Crossbar Switch
Multistage Switching Network
Hypercube Interconnection
13-3 Interprocessor Arbitration
System Bus
Serial Arbitration Procedure
Parallel Arbitration Logic
Dynamic Arbitration Algorithms
13-4 Interprocessor Communication
and Synchronization
Interprocessor Synchronization
Mutual Exclusion with a Semaphore
Problems
978813170070 (pb)
Computer Architecture.
004.22 / MAN/C
Computer system architecture / M. Morris Mano. - 2nd ed. - Englewood Cliffs, N.J. : Prentice-Hall, 2007 p. - xii, 520 p.ill.: 25 cm.
Digital Logic Circuits
1-1 Digital Computers
1-2 Logic Gates
1-3 Boolean Algebra
Complement of a Function
1-4 Map Simplification
Product-of-Sums Simplification
Don't-Care Conditions
1-5 Combinational Circuits
Half-Adder
Full-Adder
1-6 Flip-Flops
SR Flip-Flop
D Flip-Flop
JK Flip-Flop
T Flip-Flop
Edge-Triggered Flip-Flops
Excitation Tables
1-7 Sequential Circuits
Flip-Flop Input Equations
State Table
State Diagram
Design Example
Design Procedure
Problems
References
Digital Components
2-1 Integrated Circuits
2-2 Decoders
NAND Gate Decoder
Decoder Expansion
Encoders
2-3 Multiplexers
2-4 Registers
Register with Parallel Load
2-5 Shift Registers
Bidirectional Shift Register with Parallel Load
2-6 Binary Counters
Binary Counter with Parallel Load
2-7 Memory Unit
Random-Access Memory
Read-Only Memory
Types of ROMs
Problems
References
Data Representation
3-1 Data Types
Number Systems
Octal and Hexadecimal Numbers
Decimal Representation
Alphanumeric Representation
3-2 Complements
(r — l)'s Complement
(Ps) Complement
Subtraction of Unsigned Numbers
3-3 Fixed-Point Representation
Integer Representation
Aiidunetic Addition
Arithmetic Subtraction
Overflow t
Decimal Fixed-Point Representation
3-4 Floating-Point Representation
3 "5 Other Binary Codes
Gray Code
Other Decimal Codes
Other Alphanumeric Codes
3 "6 Error Detection Codes
Problems
Register Transfer and Microoperations
4" 1 Register Transfer Language
4'2 Register Transfer
4'3 Bus and Memory Transfers
Three-State Bus Buffers
Memory Transfer
4'4 Arithmetic Microoperations
Binary Adder
Binary Adder-Subtractor
Binary Incrementer
Arithmetic Circuit
4'5 Logic Microoperations
List of Logic Microoperations
Hardware Implementation
Some Apphcations
4-6 Shift Microoperations
Hardware Implementation
4-7 Arithmetic Logic Shift Unit
4'8 Hardware Description Languages
Introduction to VHDL
Basic Framework and Syntax
Problems
Basic Computer Organization and Design
5-1 Instruction Codes
Stored Program Organization
Indirect Address
5 "2 Computer Registers
Common Bus System
5'3 Computer Instructions
Instruction Set Completeness
5-4 Timing and Control
^5-5 Instruction Cycle
Fetch and Decode
Determine the Type of Instruction
Register-Reference Instructions
5-6 Memory-Reference Instructions
AND to AC
ADD to AC
IDA: Load to AC
STA: Store AC
BUN: Branch Unconditionally
BSA: Branch and Save Return Address
ISZ: Increment and Skip if Zero
Control Flowchart
5-7 Input-Output and Interrupt
Input-Output Configuration
Input-Output Instructions
Program biterrupt
Interrupt Cycle
5-8 Complete Computer Description
5-9 Design of Basic Computer
Control Logic Gates
Control of Registers and Memory
Control of Single Flip-flops
Control of Common Bus
5-10 Design of Accumulator Logic
Control of AC Register
Adder and Logic Circuit
Problems
References
Prograniming the Basic Computer
6-1 Introduction
6-2 Machine Language
6-3 Assembly Language
Rules of the Language
An Example
Translation to Binary
6'4 The Assembler
Representation of Symbolic
Program in Memory
First Pass
Second Pass
6'5 Program Loops
6-6 Programming Arithmetic and Logic Operations
Multiplication Program
Double-Precision Addition
Logic Operations
Shift Operations
6-7 Subroutines
Subroutine Parameters and
Data Linkage
6-8 Input-Output Programming
Character Manipulation
Program Interrupt
Problems
References
Microprogrammed Control
7-1 Control Memory
7-2 Address Sequencing
Conditional Branching
' Mapping of Instruction
Subroutines
7-3 Microprogram Example
Computer Configuration
Microinstruction Format
Symbolic Microinstructions
The Fetch Routine
Symbolic Microprogram
Binary Microprogram
CHAPTER EIQHT
Central Processing Unit
8-1 Introduction
8-2 General Register Organization
Control Word
Exsmplos of Microoperations
8-3 Stack Organization
Register Stack
Memory Stack
Reverse Polish Notation
Evaluation of Arithmetic Expressions
8-4 Instruction Formats
Three-Address Instructions
Two-Address Instructions
One-Address Instructions
Zero-Address Instructions
RISC Instructions
8-5 Addressing Modes
Numerical Example
8-6 E)ata Transfer and Manipulation
Data Transfer Instructions
Data Manipulation Instructions
Arithmetic Instructions
Logical and Bit Manipulation Instructions
Shift Instructions
8-7 Program Control
Status Bit Conditions
Conditional Branch Instructions
Subroutine Call and Return
Program Interrupt
Types of Interrupts —
8-8 Reduced Instruction Set Computer (RISC)
CISC Characteristics
RISC Characteristics
Contents IX
Overlapped Register Windows
Berkeley RISC I
Problems
References
Pipeline and Vector Processing
9-1 Parallel Processing
9-2 Pipelining
General Considerations
9-3 Arithmetic Pipeline
9-4 Instruction Pipeline
Example: Four-Segment Instruction Pipeline
Data Dependency
Handling of Branch Instructions
9-5 RISC Pipeline
Example: Three-Segment Instruction Pipeline
Delayed Load i
Delayed Branch
9,6 Vector Processing
Vector Operations
Matrix MultipUcation
Memory Interleaving
Superscalar Processors
Supercomputers
9-7 Anay Processors
Attached Array Processor
SIMD Array Processor
Problems
References
Computer Arithmetic
10-1 Introduction
10-2 Addition and Subtraction
Addition and Subtraction with
Signed-Magnitude Data
Hardware Implementation
Hardware Algorithm
Addition and Subtraction with
Signed-2's Complement Data
10-3 Multiplication Algorithms
Hardware Implementation for
Signed-Magnitude Data
Hardware Algorithm
Booth Multiplication Algorithm
Array Multiplier
10-4 Division Algorithms
Hardware Implementation for
Signed-Magnitude Data
Divide Overflow
Hardware Algorithm
Other Algorithms
10-5 Floating-Point Arithmetic Operations
Basic Considerations
Register Configuration
Addition and Subtraction
Multiplication
Division
10-6 Decimal Arithmetic Unit
BCD Adder
BCD Subtraction
10-7 Decimal Arithmetic Operations
Addition and Subtraction
Multiplication
Division
Floating-Point Operations
Problems
References
Input-Oulput Organization
11-1 Peripheral Devices ASCII Alphanumeric Characters
11-2 Input-Output Interface
I/O Bus and Interface Modules
I/O versus Memory Bus
Isolated versus Memory-Mapped I/O
Example of I/O Interface
11-3 Asynchronous Data Transfer
Strobe Control
Handshaking
Asynchronous Serial Transfer
Asynchronous Communication Interface
First-In, First-Out Buffer
11-4 Modes of Transfer
Example of Programmed I/O
Interrupt-Initiated I/O
Software Considerations
11-5 Priority Interrupt
Daisy-Chaining Priority
Parcel Priority Interrupt
Priority Encoder
Interrupt Cycle
Software Routines
Initial and Final Operations
11-6 Direct Memory Access (DMA)
DMA Controller
DMA Transfer
11-7 Input-Output Processor (lOP)
CPU-IOP Communication
IBM 370 I/O Channel
Intel 8089 lOP
11-8 Serial Communication
Character-oriented Protocol
Transmission Example
Data Transparency .
Bit-Oriented Protocol
Problems
References
Memory Address Map
Memory Connection to CPU
12-3 Auxiliary Memory
Magnetic Disks
Magnetic Tape
12-4 Associative Memory
Hardware Organization
Match Logic
Read Operation
Write Operation
12-5 Cache Memory
Associative Mapping
Direct Mapping
Set-Associative Mapping
Writing into Cache
Cache Initialization
12-6 Virtual Memory
Address Space and Memory Space
Address Mapping Using Pages
Associative Memory Paee Table
Page Replacement
12-7 Memory Management Hardware
Segmented-Page Mapping
Numerical Example
Memory Protection
Problems
References
Multiprocessors
13-1 Characteristics of Multiprocessors
13-2 Interconnection Structures
Time-Shared Common Bus
Multiport Memory
Crossbar Switch
Multistage Switching Network
Hypercube Interconnection
13-3 Interprocessor Arbitration
System Bus
Serial Arbitration Procedure
Parallel Arbitration Logic
Dynamic Arbitration Algorithms
13-4 Interprocessor Communication
and Synchronization
Interprocessor Synchronization
Mutual Exclusion with a Semaphore
Problems
978813170070 (pb)
Computer Architecture.
004.22 / MAN/C